Europe\u2019s largest semiconductor pilot line is now open. The NanoIC facility, based at the Interuniversity Centre for Microelectronics (imec) in Leuven, Belgium, will give researchers and chip designers across the continent access to manufacturing technology beyond the current 2-nanometer node\u2014years before that technology reaches commercial fabs.<\/p>\n\n\n\n
The project has drawn \u20ac2.5 billion in total investment. \u20ac700 million comes from national and regional governments under the EU Chips Act, with the remainder from ASML and other industry partners. It\u2019s part of a broader push to reduce European dependence on Asian and US semiconductor supply chains.<\/p>\n\n\n\n
At the center of the facility is a 2,000-square-meter cleanroom expansion, bringing imec\u2019s total cleanroom footprint above 12,000 square meters. An additional 4,000-square-meter build is planned. The site will house ASML\u2019s next-generation High NA EUV lithography system\u2014the first deployment of this machine in Europe\u2014with arrival scheduled for mid-March 2026. Over five years, more than 100 new tools will be installed across imec and partner sites in France, Germany, Finland, Ireland, and Romania.<\/p>\n\n\n\n
NanoIC has also released two process design kits (PDKs) that allow engineers to simulate future chip architectures before physical hardware exists. One targets 14-angstrom-scale logic with direct backside power delivery\u2014a method that supplies power from the back of the wafer rather than routing it through top-surface wiring. According to NanoIC\u2019s published data, this approach could produce chips that are 18% smaller and consume 7% less power at equivalent performance levels. The second PDK focuses on embedded DRAM, placing memory directly on the processor die to reduce data transfer latency\u2014a significant consideration for AI and other data-heavy workloads.<\/p>\n\n\n\n
Both toolkits are available through Europractice, an access scheme open to universities, startups, and established companies. That open-access model is deliberate. \u201cBy making these PDKs broadly accessible, we lower barriers for universities, industry, and start-ups to engage with next-generation technologies,\u201d said Giuseppe Fiorentino, NanoIC\u2019s programme manager.<\/p>\n\n\n\n
For manufacturers working with thermal processes in semiconductor production, the development is worth watching. Tighter geometries and new materials at sub-2nm scales will place higher demands on temperature uniformity, contamination control, and validated process environments throughout the fabrication chain.<\/p>\n\n\n\n